##### Project description Working for a global provider of network test monitoring and assurance solutions for telecommunications cloud enterprises first responders military aerospace and railway. a leader in light management technologies for 3D sensing anti-counterfeiting consumer electronics industrial automotive government and aerospace applications. Employees working on this project are passionate about supporting customer success and we welcome people who bring their best every day to the company – to question to collaborate and to push for solutions that will delight our customers. ##### Responsibilities We are seeking a Principal/Staff-level FPGA Engineer — a recognized technical authority — to own FPGA architecture for our state-of-the-art Communications Test & Measurement products. The successful candidate will define and drive end-to-end FPGA architecture including make/buy tradeoffs on IP floorplanning and timing closure strategy for multi-gigabit designs and DFX approach using Verilog/SystemVerilog/VHDL and industry-leading simulation synthesis place-and-route and formal/UVM verification tools. This person will serve as the final technical escalation point for FPGA design and debug issues across the team mentor other FPGA engineers and lead root-cause debug of silicon and board bring-up issues that could not be resolved elsewhere. ##### Skills Must have BS or MS degree in Electrical and/or Computer Engineering with a minimum of 12-15 years of relevant experience including at least 5+ years specifically architecting and closing timing on multi-Gbps SerDes/transceiver-based FPGA designs. Demonstrated expertise architecting and implementing high-speed FPGA designs using Verilog/SystemVerilog and/or VHDL required. Deep hands-on expertise with FPGA transceivers hard IP and PLLs — including timing closure equalization and link debug at multi-Gbps rates — required (not incidental exposure). Demonstrated experience closing timing and debugging link-layer issues on high-speed Ethernet (10M to 1.6T) and IP protocol stacks in production designs. Proven expertise with optical interfaces and modules (SFPs QSFPs) in shipped products. Deep working knowledge of VLANs MPLS VPLS and Voice/Video over IP (VoIP IPTV). Extensive experience with AMD or Altera FPGA devices and their full implementation toolchains including advanced timing closure and floorplanning techniques. Proven experience with formal verification and/or UVM-based verification methodologies not limited to directed testbenches. Demonstrated track record of taking FPGA designs from architecture through volume production including systems-level tradeoffs across the HW/FW boundary. Version control experience using Git or similar tools. Exceptional written and oral communication skills including the ability to mentor engineers and communicate architecture decisions with stakeholders across the world. Exceptional analytical and organizational skills with an uncompromising commitment to accuracy and technical rigor in a fast-paced product environment. Nice to have Patents or published work in FPGA architecture high-speed digital design or DSP. Experience defining test strategies for multi-Gbps compliance testing (particularly relevant for T&M product development). General purpose microprocessor and DSP systems PCIe high-speed digital board design PLL design and analog signal conditioning experience. Simulation experience using Siemens Questa Aldec Riviera or similar tools. Contribution to or deep familiarity with open verification methodologies (e.g. cocotb UVM community contributions). Utilization of generative AI tools to assist in concept and implementation of FPGA designs. ##### Other Languages English B2 Upper Intermediate Seniority Lead Remote India India Req. VR-124323 C/C++ Cross Industry Solutions 31/07/2026 Req. VR-124323