EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power energy and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. We are an ambitious AI hardware startup building next-generation accelerators with massive compute density. To achieve aggressive Power Performance and Area (PPA) targets on accelerated tapeout schedules we require a robust highly automated and heavily optimized physical implementation and signoff flow. The Role As a Staff / Senior Staff CAD & Methodology Engineer you will be the resident expert in Innovus and Tempus responsible for developing debugging and continually accelerating our RTL-to-GDSII and timing signoff flows. You will work closely with Physical Design and STA leads to eliminate bottlenecks automate manual tasks and push the limits of EDA capabilities at advanced process nodes. Key Responsibilities Flow Architecture & Automation Architect develop and maintain a highly automated robust and scalable physical design and signoff flow from synthesis through GDSII optimized for AI accelerator architectures. Innovus Methodology Drive advanced physical design methodologies in Cadence Innovus. Optimize recipes for floorplanning placement Clock Tree Synthesis (CTS) routing and power grid implementation to squeeze out maximum PPA. Tempus Signoff Integration Own the STA and timing signoff methodology using Cadence Tempus. Implement and optimize Distributed Multi-Scenario Analysis (DMSA) advanced OCV methodologies and automated Tempus ECO flows to ensure rapid timing closure. Turnaround Time (TAT) Reduction Identify inefficiencies in the daily execution of block and top-level implementation. Develop Python and Tcl-based automation database parsers and custom utilities to drastically reduce tool runtime and engineering debug time. Tool & Vendor Interface Act as the primary technical liaison with Cadence. Drive tool evaluations beta testing of new features and resolution of critical tool bugs or limitations to ensure continuous flow stability. Mentorship & Support Serve as the final escalation point for the PD and Timing teams regarding flow-related issues. Document methodologies clearly and mentor junior engineers on tool usage and flow mechanics. Requirements & Qualifications Experience 9 to 14 years of industry experience in ASIC/SOC physical design with a primary focus on CAD TFM (Tools Flows and Methodology) or flow automation. Cadence Mastery Deep production-proven expertise with Cadence Innovus (Implementation) and Cadence Tempus (Signoff STA). Strong understanding of internal tool mechanics database access commands (dbGet) and advanced tool configuration. Scripting & Software Skills Expert-level proficiency in Tcl and Python. Strong background in Makefile generation shell scripting and version control (Git/Perforce). Domain Knowledge Thorough understanding of deep sub-micron physical design concepts (advanced node DRCs cross-talk electromigration IR drop) and the theoretical foundations of Static Timing Analysis. Startup Mindset Ability to thrive in a fast-paced dynamic environment where flow requirements evolve rapidly as the architecture matures. Education Bachelor’s or Master’s degree in Electrical Engineering Computer Science Computer Engineering or a related discipline.